1. Field of the Invention
This invention is directed toward methods and apparatus for monitoring damage on microelectronic devices brought on by processing steps. More particularly, the invention is directed toward the use of a current-voltage, or a cyclic current-voltage measurement system to monitor processing, to quantify damage and to monitor the correction (i.e. annealing) of the damage by means of subsequent processing steps.
2. Background of the Art
Dielectric/semiconductor systems are widely used, and are of great importance, in the microelectronics industries. Such systems include ultrathin layers such as SiO.sub.2 /Si materials systems. Such ultrathin SiO.sub.2 /Si systems are particularly difficult to monitor and characterize using prior art capacitive-voltage (C-V) monitoring techniques because C-V measurements for such thin SiO.sub.2 layers are severely hampered by the presence of high conductance in ultrathin dielectric structures. This results in interpretation of C-V results becoming relatively complex.
Another prior art technique used to study and monitor dielectric/semiconductor interfaces is the deep level transient spectroscopy (DLTS) technique. The DLTS technique can, however, only probe the semiconductor material in the system and, therefore, does not provide any information on the critical SiO.sub.2 /Si interface, and the SiO.sub.2 itself. In addition, DLTS is relatively slow and requires cooling to cryogenic temperatures.
Attention is now directed to prior art systems or procedures for specifically monitoring damage on microelectronic devices brought on by plasma processing steps. The CHARM technique uses floating gate memory devices (EEPROMs) to monitor the surface potential and the ultraviolet (UV) exposure during processing. CHARM does not provide any information on direct plasma exposure damage, since all devices are encapsulated and they are never exposed directly to the plasma being studied. Furthermore, the CHARM devices are complex and the processing involved in their fabrication is lengthy and therefore costly. SPIDER plasma processing monitoring wafers evaluate the overall impact of processing on individual transistors, and monitor charging damage through the use of antenna structures. SPIDER, like CHARM, requires lengthy, costly processing for its fabrication. In addition, both CHARM and SPIDER use time consuming terminal measurements of devices after exposure to determine the extent of any detrimental processing exposure effects.
In view of the summarized prior procedures above, an object of the present invention is to provide a simple, two-terminal measurement of easily fabricated test structures for monitoring the impact of processing of typical ultrathin and other microelectronic devices, such as ultrathin SiO.sub.2 /Si systems. This measurement technique eliminates problems in C-V measurements resulting from the high conductance of the ultrathin SiO.sub.2.
Another object of the present invention is to provide a technique for interrogating all of the interface states of an ultrathin device such as a SiO.sub.2 /Si device, at the interface.
An additional object of the present invention is to provide a two terminal monitoring systems which yields results which are easily and quickly interpreted.
One benefit of the present invention is to provide a monitoring system which can be operated at room temperature.
Another object of the invention is to provide a system which can fully characterize the dielectric/semiconductor interface, unlike the DLTS which can not access the interface directly but only access the semiconductor portion of the device.
Yet another object of the present invention is to provide a monitoring system which can be used in a contact-free mode, wherein the dielectric/semiconductor interface is characterized by using a contact free probe which is positioned extremely close to the surface of the device, and the probe/air or a probe/insulator region is flux coupled to an ultrathin system such as a SiO.sub.2 /Si materials system.
An additional object of the invention is to provide a technique with which the carrier lifetimes in the semiconductor can be determined conveniently from the near surface region as devices are built.
There are other objects and advantages of the present invention which will become apparent in the following disclosure.